ASTRON & IBM Center for Exascale Technology


Work at the Zurich Research lab over the last few years has shown that the Instructions Set Architecture (ISA) of a specific computer chip is not resulting in a noticeable difference in energy-required-per-answer (Intel Atom, ARM, PPC). Benchmarks using standard software to generate answers from data were characterized for power-per answer, with a result that there is no noticeable difference in energy-per-answer, using single cores in 45nm CMOS.

Novel packaging technology developed at the IBM Research lab allows highly efficient water cooling of Processor-, Memory- and voltage-controller components. The microserver project, in a first stage will aim at achieving the highest computer packaging density, including cooling, until today.

In a subsequent step, IBM developed 3-dimensional packaging (Processor chips, and memory chips packaged together, with cooling) will be used to achieve even higher densities of compute power.

This is will define achievable and aggressive datapoints in compute density and compute performance per Watt – which is one of the outstanding challenges for SKA. The proposed prototypes of this microserver will be used at ASTRON in a real-life environment (LOFAR data) to get early feedback on operation. The highly parallel character of these microservers requires also a step-change in algorithm design and software development – a key component of future knowledge economies for computer application design. It is expected that also commercial workloads as Hadoop (Google) will be interested in this type of technology.